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corefreqk.h
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/*
* CoreFreq
* Copyright (C) 2015-2021 CYRIL INGENIERIE
* Licenses: GPL2
*/
#define RDCOUNTER(_val, _cnt) \
({ \
unsigned int _lo, _hi; \
\
__asm__ volatile \
( \
"rdmsr" \
: "=a" (_lo), \
"=d" (_hi) \
: "c" (_cnt) \
); \
_val=_lo | ((unsigned long long) _hi << 32); \
})
#define WRCOUNTER(_val, _cnt) \
__asm__ volatile \
( \
"wrmsr" \
: \
: "c" (_cnt), \
"a" ((unsigned int) _val & 0xFFFFFFFF), \
"d" ((_val > 0xFFFFFFFF) ? \
(unsigned int) (_val >> 32) : 0) \
);
#define RDMSR(_data, _reg) \
({ \
unsigned int _lo, _hi; \
\
__asm__ volatile \
( \
"rdmsr" \
: "=a" (_lo), \
"=d" (_hi) \
: "c" (_reg) \
); \
_data.value=_lo | ((unsigned long long) _hi << 32); \
})
#define WRMSR(_data, _reg) \
__asm__ volatile \
( \
"wrmsr" \
: \
: "c" (_reg), \
"a" ((unsigned int) _data.value & 0xFFFFFFFF), \
"d" ((unsigned int) (_data.value >> 32)) \
);
#define RDMSR64(_data, _reg) \
__asm__ volatile \
( \
"xorq %%rax, %%rax" "\n\t" \
"xorq %%rdx, %%rdx" "\n\t" \
"movq %1,%%rcx" "\n\t" \
"rdmsr" "\n\t" \
"shlq $32, %%rdx" "\n\t" \
"orq %%rdx, %%rax" "\n\t" \
"movq %%rax, %0" \
: "=m" (_data) \
: "i" (_reg) \
: "%rax", "%rcx", "%rdx" \
)
#define WRMSR64(_data, _reg) \
__asm__ volatile \
( \
"movq %0, %%rax" "\n\t" \
"movq %%rax, %%rdx" "\n\t" \
"shrq $32, %%rdx" "\n\t" \
"movq %1, %%rcx" "\n\t" \
"wrmsr" \
: "=m" (_data) \
: "i" (_reg) \
: "%rax", "%rcx", "%rdx" \
)
#define Atomic_Read_VPMC(_lock, _dest, _src) \
{ \
__asm__ volatile \
( \
"xorq %%rax , %%rax" "\n\t" \
_lock "cmpxchg %%rax , %[src]" "\n\t" \
"movq %%rax , %[dest]" \
: [dest] "=m" (_dest) \
: [src] "m" (_src) \
: "%rax", "cc", "memory" \
); \
}
#define Atomic_Add_VPMC(_lock, _dest, _src) \
{ \
__asm__ volatile \
( \
"xorq %%rax , %%rax" "\n\t" \
_lock "cmpxchg %%rax , %[src]" "\n\t" \
"addq %%rax , %[dest]" \
: [dest] "=m" (_dest) \
: [src] "m" (_src) \
: "%rax", "cc", "memory" \
); \
}
#define ASM_CODE_RDMSR(_msr, _reg) \
"# Read MSR counter." "\n\t" \
"movq $" #_msr ", %%rcx" "\n\t" \
"rdmsr" "\n\t" \
"shlq $32, %%rdx" "\n\t" \
"orq %%rdx, %%rax" "\n\t" \
"# Save counter value." "\n\t" \
"movq %%rax, %%" #_reg "\n\t"
#define ASM_RDMSR(_msr, _reg) ASM_CODE_RDMSR(_msr, _reg)
#define ASM_COUNTERx1( _reg0, _reg1, \
_tsc_inst, mem_tsc, \
_msr1, _mem1) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" \
: "=m" (mem_tsc), "=m" (_mem1) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", \
"cc", "memory" \
);
#define ASM_COUNTERx2( _reg0, _reg1, _reg2, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", \
"cc", "memory" \
);
#define ASM_COUNTERx3( _reg0, _reg1, _reg2, _reg3, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"cc", "memory" \
);
#define ASM_COUNTERx4( _reg0, _reg1, _reg2, _reg3, _reg4, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", \
"cc", "memory" \
);
#define ASM_COUNTERx5( _reg0, _reg1, _reg2, _reg3, _reg4, _reg5, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
ASM_RDMSR(_msr5, _reg5) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" "\n\t" \
"movq %%" #_reg5 ", %5" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", "%" #_reg5"", \
"cc", "memory" \
);
#define ASM_COUNTERx5_STACK(_reg0, _reg1, _reg2, _reg3, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr4, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr5, _reg3) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %5" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %4" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %3" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"cc", "memory" \
);
#define ASM_COUNTERx6( _reg0, _reg1, _reg2, _reg3, _reg4, _reg5, _reg6,\
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
ASM_RDMSR(_msr5, _reg5) \
ASM_RDMSR(_msr6, _reg6) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" "\n\t" \
"movq %%" #_reg5 ", %5" "\n\t" \
"movq %%" #_reg6 ", %6" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", "%" #_reg5"", "%" #_reg6"", \
"cc", "memory" \
);
#define ASM_COUNTERx6_STACK(_reg0, _reg1, _reg2, _reg3, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr4, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr5, _reg3) \
"pushq %%" #_reg3 "\n\t" \
ASM_RDMSR(_msr6, _reg3) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %6" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %5" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %4" "\n\t" \
"popq %%" #_reg3 "\n\t" \
"movq %%" #_reg3 ", %3" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"cc", "memory" \
);
#define ASM_COUNTERx7( _reg0, _reg1, _reg2, _reg3, \
_reg4, _reg5, _reg6, _reg7, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6, \
_msr7, _mem7) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
ASM_RDMSR(_msr3, _reg3) \
ASM_RDMSR(_msr4, _reg4) \
ASM_RDMSR(_msr5, _reg5) \
ASM_RDMSR(_msr6, _reg6) \
ASM_RDMSR(_msr7, _reg7) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %2" "\n\t" \
"movq %%" #_reg3 ", %3" "\n\t" \
"movq %%" #_reg4 ", %4" "\n\t" \
"movq %%" #_reg5 ", %5" "\n\t" \
"movq %%" #_reg6 ", %6" "\n\t" \
"movq %%" #_reg7 ", %7" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6), "=m" (_mem7) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", "%" #_reg3"", \
"%" #_reg4"", "%" #_reg5"", "%" #_reg6"", "%" #_reg7"", \
"cc", "memory" \
);
#define ASM_COUNTERx7_STACK(_reg0, _reg1, _reg2, \
_tsc_inst, mem_tsc, \
_msr1, _mem1, _msr2, _mem2, _msr3, _mem3, \
_msr4, _mem4, _msr5, _mem5, _msr6, _mem6, \
_msr7, _mem7) \
__asm__ volatile \
( \
_tsc_inst(_reg0) \
ASM_RDMSR(_msr1, _reg1) \
ASM_RDMSR(_msr2, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr3, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr4, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr5, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr6, _reg2) \
"pushq %%" #_reg2 "\n\t" \
ASM_RDMSR(_msr7, _reg2) \
"# Store values into memory." "\n\t" \
"movq %%" #_reg0 ", %0" "\n\t" \
"movq %%" #_reg1 ", %1" "\n\t" \
"movq %%" #_reg2 ", %7" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %6" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %5" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %4" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %3" "\n\t" \
"popq %%" #_reg2 "\n\t" \
"movq %%" #_reg2 ", %2" \
: "=m" (mem_tsc), "=m" (_mem1), "=m" (_mem2), "=m" (_mem3), \
"=m" (_mem4), "=m" (_mem5), "=m" (_mem6), "=m" (_mem7) \
: \
: "%rax", "%rcx", "%rdx", \
"%" #_reg0"", "%" #_reg1"", "%" #_reg2"", \
"cc", "memory" \
);
#define RDTSC_COUNTERx1(mem_tsc, ...) \
ASM_COUNTERx1(r10, r11, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx1(mem_tsc, ...) \
ASM_COUNTERx1(r10, r11, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx2(mem_tsc, ...) \
ASM_COUNTERx2(r10, r11, r12, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx2(mem_tsc, ...) \
ASM_COUNTERx2(r10, r11, r12, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx3(mem_tsc, ...) \
ASM_COUNTERx3(r10, r11, r12, r13, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx3(mem_tsc, ...) \
ASM_COUNTERx3(r10, r11, r12, r13, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx4(mem_tsc, ...) \
ASM_COUNTERx4(r10, r11, r12, r13, r14, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx4(mem_tsc, ...) \
ASM_COUNTERx4(r10, r11, r12, r13, r14, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#if defined(OPTIM_LVL) && OPTIM_LVL == 0
#define RDTSC_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5_STACK(r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5_STACK(r12, r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6_STACK(r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6_STACK(r12, r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7_STACK(r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7_STACK(r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#else
/* #warning "Optimization" */
#define RDTSC_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5(r10, r11, r12, r13, r14, r15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx5(mem_tsc, ...) \
ASM_COUNTERx5(r10, r11, r12, r13, r14, r15, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
#define RDTSC_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6(r10, r11, r12, r13, r14, r15, r9, ASM_RDTSC, mem_tsc, __VA_ARGS__)
#define RDTSCP_COUNTERx6(mem_tsc, ...) \
ASM_COUNTERx6(r10, r11, r12, r13, r14, r15, r9, ASM_RDTSCP, mem_tsc,__VA_ARGS__)
#define RDTSC_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7(r10, r11, r12, r13, r14, r15,r9,r8,ASM_RDTSC,mem_tsc,__VA_ARGS__)
#define RDTSCP_COUNTERx7(mem_tsc, ...) \
ASM_COUNTERx7(r10, r11, r12, r13, r14, r15,r9,r8,ASM_RDTSCP,mem_tsc,__VA_ARGS__)
#endif
#define PCI_CONFIG_ADDRESS(bus, dev, fn, reg) \
(0x80000000 | ((bus) << 16)|((dev) << 11)|((fn) << 8)|((reg) & ~3))
#define RDPCI(_data, _reg) \
({ \
__asm__ volatile \
( \
"movl %1, %%eax" "\n\t" \
"movl $0xcf8, %%edx" "\n\t" \
"outl %%eax, %%dx" "\n\t" \
"movl $0xcfc, %%edx" "\n\t" \
"inl %%dx, %%eax" "\n\t" \
"movl %%eax, %0" \
: "=m" (_data) \
: "ir" (_reg) \
: "%rax", "%rdx", "memory" \
); \
})
#define WRPCI(_data, _reg) \
({ \
__asm__ volatile \
( \
"movl %1, %%eax" "\n\t" \
"movl $0xcf8, %%edx" "\n\t" \
"outl %%eax, %%dx" "\n\t" \
"movl %0, %%eax" "\n\t" \
"movl $0xcfc, %%edx" "\n\t" \
"outl %%eax, %%dx" \
: \
: "irm" (_data), \
"ir" (_reg) \
: "%rax", "%rdx", "memory" \
); \
})
/* Manufacturers Identifier Strings. */
#define VENDOR_INTEL "GenuineIntel"
#define VENDOR_AMD "AuthenticAMD"
#define VENDOR_HYGON "HygonGenuine"
#define VENDOR_KVM "TCGTGTCGCGTC"
#define VENDOR_VBOX "VBoxVBoxVBox"
#define VENDOR_KBOX "KVMKM"
#define VENDOR_VMWARE "VMwawarereVM"
#define VENDOR_HYPERV "Micrt Hvosof"
/* Source: Winbond W83627 and ITE IT8720F datasheets */
#define HWM_SIO_INDEX_PORT 0x295
#define HWM_SIO_DATA_PORT 0x296
#define HWM_SIO_CPUVCORE 0x20
#define RDSIO(_data, _reg, _index_port, _data_port) \
({ \
__asm__ volatile \
( \
"movw %1, %%ax" "\n\t" \
"movw %2, %%dx" "\n\t" \
"outw %%ax, %%dx" "\n\t" \
"movw %3, %%dx" "\n\t" \
"inb %%dx, %%al" "\n\t" \
"movb %%al, %0" \
: "=m" (_data) \
: "i" (_reg) , \
"i" (_index_port), \
"i" (_data_port) \
: "%ax", "%dx", "memory" \
); \
})
/* Hardware Monitoring: Super I/O chipset identifiers */
#define COMPATIBLE 0xffff
#define W83627 0x5ca3
#define IT8720 0x8720
/*
* --- Core_AMD_SMN_Read and Core_AMD_SMN_Write ---
*
* amd_smn_read() and amd_smn_write() protect any SMU access through
* mutex_[un]lock functions which must not be used in interrupt context.
*
* The high resolution timers are bound to CPUs using smp_call_function_*
* where context is interrupt; and where mutexes will freeze the kernel.
*/
#if defined(CONFIG_AMD_NB) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0))\
&& defined(LEGACY) && (LEGACY > 1)
FEAT_MSG("LEGACY Level 2: built with amd_smn_read(), amd_smn_write()")
#define Core_AMD_SMN_Read( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
if (PRIVATE(OF(ZenIF_dev)) != NULL) \
{ \
if (amd_smn_read(amd_pci_dev_to_node_id(PRIVATE(OF(ZenIF_dev))),\
SMN_Address, &SMN_Register.value)) \
{ \
pr_warn("CoreFreq: Failed to read amd_smn_read()\n"); \
} \
} \
})
#define Core_AMD_SMN_Write( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
if (PRIVATE(OF(ZenIF_dev)) != NULL) \
{ \
if (amd_smn_write(amd_pci_dev_to_node_id(PRIVATE(OF(ZenIF_dev))),\
SMN_Address, &SMN_Register.value)) \
{ \
pr_warn("CoreFreq: Failed to write amd_smn_write()\n"); \
} \
} \
})
#else
#define Core_AMD_SMN_Read( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
unsigned int tries = BIT_IO_RETRIES_COUNT; \
unsigned char ret; \
do { \
ret = BIT_ATOM_TRYLOCK( BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED ); \
if ( ret == 0 ) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} else { \
WRPCI(SMN_Address, SMU_IndexRegister); \
RDPCI(SMN_Register.value, SMU_DataRegister); \
\
BIT_ATOM_UNLOCK(BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED); \
} \
tries--; \
} while ( (tries != 0) && (ret != 1) ); \
if (tries == 0) { \
pr_warn("CoreFreq: Core_AMD_SMN_Read(%x, %x) TryLock\n", \
SMN_Register.value, SMN_Address); \
} \
})
#define Core_AMD_SMN_Write( SMN_Register, \
SMN_Address, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
unsigned int tries = BIT_IO_RETRIES_COUNT; \
unsigned char ret; \
do { \
ret = BIT_ATOM_TRYLOCK( BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED ); \
if ( ret == 0 ) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} else { \
WRPCI(SMN_Address, SMU_IndexRegister); \
WRPCI(SMN_Register.value, SMU_DataRegister); \
\
BIT_ATOM_UNLOCK(BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED); \
} \
tries--; \
} while ( (tries != 0) && (ret != 1) ); \
if (tries == 0) { \
pr_warn("CoreFreq: Core_AMD_SMN_Write(%x, %x) TryLock\n", \
SMN_Register.value, SMN_Address); \
} \
})
#endif /* CONFIG_AMD_NB and LEGACY */
typedef union
{
unsigned int value;
struct
{
unsigned int
bits : 32-0;
};
} HSMP_ARG;
#define AMD_HSMP_Mailbox( MSG_FUNC, \
MSG_ARG, \
HSMP_CmdRegister, \
HSMP_ArgRegister, \
HSMP_RspRegister, \
SMU_IndexRegister, \
SMU_DataRegister ) \
({ \
HSMP_ARG MSG_RSP = {.value = 0x0}; \
HSMP_ARG MSG_ID = {.value = MSG_FUNC}; \
unsigned int tries = BIT_IO_RETRIES_COUNT; \
unsigned char ret; \
do { \
ret = BIT_ATOM_TRYLOCK( BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED ); \
if ( ret == 0 ) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} \
else \
{ \
unsigned int idx; \
unsigned char wait; \
\
WRPCI(HSMP_RspRegister , SMU_IndexRegister); \
WRPCI(MSG_RSP.value , SMU_DataRegister); \
\
for (idx = 0; idx < 8; idx++) { \
WRPCI(HSMP_ArgRegister + (idx << 2), SMU_IndexRegister);\
WRPCI(MSG_ARG[idx].value, SMU_DataRegister); \
} \
WRPCI(HSMP_CmdRegister , SMU_IndexRegister); \
WRPCI(MSG_ID.value , SMU_DataRegister); \
\
idx = BIT_IO_RETRIES_COUNT; \
do { \
WRPCI(HSMP_RspRegister , SMU_IndexRegister); \
RDPCI(MSG_RSP.value , SMU_DataRegister); \
\
idx--; \
wait = (idx != 0) && (MSG_RSP.value == 0x0) ? 1 : 0; \
if (wait == 1) { \
udelay(BIT_IO_DELAY_INTERVAL); \
} \
} while (wait == 1); \
if (idx == 0) { \
pr_warn("CoreFreq: AMD_HSMP_Mailbox(%x) Timeout\n", \
MSG_FUNC); \
} \
else if (MSG_RSP.value == 0x1) \
{ \
for (idx = 0; idx < 8; idx++) { \
WRPCI(HSMP_ArgRegister + (idx << 2), SMU_IndexRegister);\
RDPCI(MSG_ARG[idx].value, SMU_DataRegister); \
} \
} \
BIT_ATOM_UNLOCK(BUS_LOCK, \
PRIVATE(OF(AMD_SMN_LOCK)), \
ATOMIC_SEED); \
} \
tries--; \
} while ( (tries != 0) && (ret != 1) ); \
if (tries == 0) { \
pr_warn("CoreFreq: AMD_HSMP_Mailbox(%x) TryLock\n", MSG_FUNC); \
} \
MSG_RSP.value; \
})
/* Driver' private and public data definitions. */
enum CSTATES_CLASS {
CSTATES_NHM,
CSTATES_SNB,
CSTATES_ULT,
CSTATES_SKL,
CSTATES_SOC_SLM,
CSTATES_SOC_GDM
};
#define LATCH_NONE 0b0000
#define LATCH_TGT_RATIO_UNLOCK 0b0001 /* <T> TgtRatioUnlocked */
#define LATCH_CLK_RATIO_UNLOCK 0b0010 /* <X> ClkRatioUnlocked */
#define LATCH_TURBO_UNLOCK 0b0100 /* <B> TurboUnlocked */
#define LATCH_UNCORE_UNLOCK 0b1000 /* <U> UncoreUnlocked */
typedef struct {
char *CodeName;
} MICRO_ARCH;
typedef struct {
char **Brand;
unsigned int Boost[2];
THERMAL_PARAM Param;
unsigned int CodeNameIdx : 8-0,
TgtRatioUnlocked: 9-8, /* <T:1> */
ClkRatioUnlocked: 11-9, /* <X:2> */
TurboUnlocked : 12-11, /* <B:1> */
UncoreUnlocked : 13-12, /* <U:1> */
_UnusedSpecBits : 28-13,
Latch : 32-28; /* <U>-<B>-<X>-<T> */
} PROCESSOR_SPECIFIC;
typedef struct {
FEATURES *Features;
char *Brand;
unsigned int SMT_Count,
localProcessor;
signed int rc;
} INIT_ARG;
typedef struct { /* V[0] stores the previous TSC */
unsigned long long V[2]; /* V[1] stores the current TSC */
} TSC_STRUCT;
#define OCCURRENCES 4
/* OCCURRENCES x 2 (TSC values) needs a 64-byte cache line size. */
#define STRUCT_SIZE (OCCURRENCES * sizeof(TSC_STRUCT))
typedef struct {
TSC_STRUCT *TSC[2];
CLOCK Clock;
} COMPUTE_ARG;
typedef struct
{
PROC_RO *Proc_RO;
PROC_RW *Proc_RW;
SYSGATE_RO *Gate;
struct kmem_cache *Cache;
CORE_RO **Core_RO;
CORE_RW **Core_RW;
} KPUBLIC;
enum { CREATED, STARTED, MUSTFWD };
typedef struct
{
struct hrtimer Timer;
/*
TSM: Timer State Machine
CREATED: 1-0
STARTED: 2-1
MUSTFWD: 3-2
*/
Bit64 TSM __attribute__ ((aligned (8)));
} JOIN;
typedef struct
{
PROCESSOR_SPECIFIC *Specific;
#ifdef CONFIG_AMD_NB
struct pci_dev *ZenIF_dev;
#endif
Bit64 AMD_SMN_LOCK __attribute__ ((aligned (8)));
Bit64 AMD_FCH_LOCK __attribute__ ((aligned (8)));
struct kmem_cache *Cache;
JOIN *Join[];
} KPRIVATE;
/* Sources:
* Intel® 64 and IA-32 Architectures Software Developer’s Manual; Vol. 2A
* AMD64 Architecture Programmer’s Manual; Vol. 3
*/
static const CPUID_STRUCT CpuIDforVendor[CPUID_MAX_FUNC] = {
/* x86 */
[CPUID_00000001_00000000_INSTRUCTION_SET]
= {.func = 0x00000001, .sub = 0x00000000},
/* Intel */
[CPUID_00000002_00000000_CACHE_AND_TLB]
= {.func = 0x00000002, .sub = 0x00000000},
[CPUID_00000003_00000000_PROC_SERIAL_NUMBER]
= {.func = 0x00000003, .sub = 0x00000000},
[CPUID_00000004_00000000_CACHE_L1I]
= {.func = 0x00000004, .sub = 0x00000000},
[CPUID_00000004_00000001_CACHE_L1D]
= {.func = 0x00000004, .sub = 0x00000001},
[CPUID_00000004_00000002_CACHE_L2]
= {.func = 0x00000004, .sub = 0x00000002},
[CPUID_00000004_00000003_CACHE_L3]
= {.func = 0x00000004, .sub = 0x00000003},
/* x86 */
[CPUID_00000005_00000000_MONITOR_MWAIT]
= {.func = 0x00000005, .sub = 0x00000000},
[CPUID_00000006_00000000_POWER_AND_THERMAL_MGMT]
= {.func = 0x00000006, .sub = 0x00000000},
[CPUID_00000007_00000000_EXTENDED_FEATURES]
= {.func = 0x00000007, .sub = 0x00000000},
[CPUID_00000007_00000001_EXT_FEAT_SUB_LEAF_1]
= {.func = 0x00000007, .sub = 0x00000001},
/* Intel */
[CPUID_00000009_00000000_DIRECT_CACHE_ACCESS]
= {.func = 0x00000009, .sub = 0x00000000},
[CPUID_0000000A_00000000_PERF_MONITORING]
= {.func = 0x0000000a, .sub = 0x00000000},
/* x86 */
[CPUID_0000000B_00000000_EXT_TOPOLOGY]
= {.func = 0x0000000b, .sub = 0x00000000},
[CPUID_0000000D_00000000_EXT_STATE_MAIN_LEAF]
= {.func = 0x0000000d, .sub = 0x00000000},
[CPUID_0000000D_00000001_EXT_STATE_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x00000001},
/* AMD */
[CPUID_0000000D_00000002_EXT_STATE_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x00000002},
[CPUID_0000000D_00000003_BNDREGS_STATE]
= {.func = 0x0000000d, .sub = 0x00000003},
[CPUID_0000000D_00000004_BNDCSR_STATE]
= {.func = 0x0000000d, .sub = 0x00000004},
/* AMD Family 19h */
[CPUID_0000000D_00000009_MPK_STATE_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x00000009},
[CPUID_0000000D_00000009_CET_U_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x0000000b},
[CPUID_0000000D_00000009_CET_S_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x0000000c},
/* AMD Family 15h */
[CPUID_0000000D_0000003E_EXT_STATE_SUB_LEAF]
= {.func = 0x0000000d, .sub = 0x0000003e},
/* Intel */
[CPUID_0000000F_00000000_QOS_MONITORING_CAP]
= {.func = 0x0000000f, .sub = 0x00000000},
[CPUID_0000000F_00000001_L3_QOS_MONITORING]
= {.func = 0x0000000f, .sub = 0x00000001},
[CPUID_00000010_00000000_QOS_ENFORCEMENT_CAP]
= {.func = 0x00000010, .sub = 0x00000000},
[CPUID_00000010_00000001_L3_ALLOC_ENUMERATION]
= {.func = 0x00000010, .sub = 0x00000001},
[CPUID_00000010_00000002_L2_ALLOC_ENUMERATION]
= {.func = 0x00000010, .sub = 0x00000002},
[CPUID_00000010_00000003_RAM_BANDWIDTH_ENUM]
= {.func = 0x00000010, .sub = 0x00000003},
[CPUID_00000012_00000000_SGX_CAPABILITY]
= {.func = 0x00000012, .sub = 0x00000000},
[CPUID_00000012_00000001_SGX_ATTRIBUTES]
= {.func = 0x00000012, .sub = 0x00000001},
[CPUID_00000012_00000002_SGX_ENCLAVE_PAGE_CACHE]
= {.func = 0x00000012, .sub = 0x00000002},
[CPUID_00000014_00000000_PROCESSOR_TRACE]
= {.func = 0x00000014, .sub = 0x00000000},
[CPUID_00000014_00000001_PROC_TRACE_SUB_LEAF]
= {.func = 0x00000014, .sub = 0x00000001},
[CPUID_00000015_00000000_TIME_STAMP_COUNTER]
= {.func = 0x00000015, .sub = 0x00000000},
[CPUID_00000016_00000000_PROCESSOR_FREQUENCY]
= {.func = 0x00000016, .sub = 0x00000000},
[CPUID_00000017_00000000_SYSTEM_ON_CHIP]
= {.func = 0x00000017, .sub = 0x00000000},
[CPUID_00000017_00000001_SOC_ATTRIB_SUB_LEAF_1]
= {.func = 0x00000017, .sub = 0x00000001},
[CPUID_00000017_00000002_SOC_ATTRIB_SUB_LEAF_2]
= {.func = 0x00000017, .sub = 0x00000002},
[CPUID_00000017_00000003_SOC_ATTRIB_SUB_LEAF_3]
= {.func = 0x00000017, .sub = 0x00000003},
/* Intel */
[CPUID_00000018_00000000_ADDRESS_TRANSLATION]
= {.func = 0x00000018, .sub = 0x00000000},
[CPUID_00000018_00000001_DAT_SUB_LEAF_1]
= {.func = 0x00000018, .sub = 0x00000001},
[CPUID_00000019_00000000_KEY_LOCKER]
= {.func = 0x00000019, .sub = 0x00000000},
[CPUID_0000001A_00000000_HYBRID_INFORMATION]
= {.func = 0x0000001a, .sub = 0x00000000},
[CPUID_0000001B_00000000_PCONFIG_INFORMATION]
= {.func = 0x0000001b, .sub = 0x00000000},
[CPUID_0000001F_00000000_EXT_TOPOLOGY_V2]
= {.func = 0x0000001f, .sub = 0x00000000},
/* x86 */
[CPUID_80000001_00000000_EXTENDED_FEATURES]
= {.func = 0x80000001, .sub = 0x00000000},
[CPUID_80000002_00000000_PROCESSOR_NAME_ID]
= {.func = 0x80000002, .sub = 0x00000000},
[CPUID_80000003_00000000_PROCESSOR_NAME_ID]
= {.func = 0x80000003, .sub = 0x00000000},
[CPUID_80000004_00000000_PROCESSOR_NAME_ID]
= {.func = 0x80000004, .sub = 0x00000000},
/* AMD */
[CPUID_80000005_00000000_CACHES_L1D_L1I_TLB]
= {.func = 0x80000005, .sub=0x00000000},
/* x86 */
[CPUID_80000006_00000000_CACHE_L2_SIZE_WAY]
= {.func = 0x80000006, .sub = 0x00000000},
[CPUID_80000007_00000000_ADVANCED_POWER_MGMT]
= {.func = 0x80000007, .sub = 0x00000000},
[CPUID_80000008_00000000_LM_ADDRESS_SIZE]
= {.func = 0x80000008, .sub = 0x00000000},
/* AMD */
[CPUID_8000000A_00000000_SVM_REVISION]
= {.func = 0x8000000a, .sub = 0x00000000},
[CPUID_80000019_00000000_CACHES_AND_TLB_1G]
= {.func = 0x80000019, .sub = 0x00000000},
[CPUID_8000001A_00000000_PERF_OPTIMIZATION]
= {.func = 0x8000001a, .sub = 0x00000000},
[CPUID_8000001B_00000000_INST_BASED_SAMPLING]
= {.func = 0x8000001b, .sub = 0x00000000},
[CPUID_8000001C_00000000_LIGHTWEIGHT_PROFILING]
= {.func = 0x8000001c, .sub = 0x00000000},
[CPUID_8000001D_00000000_CACHE_L1D_PROPERTIES]
= {.func = 0x8000001d, .sub = 0x00000000},
[CPUID_8000001D_00000001_CACHE_L1I_PROPERTIES]
= {.func = 0x8000001d, .sub = 0x00000001},
[CPUID_8000001D_00000002_CACHE_L2_PROPERTIES]
= {.func = 0x8000001d, .sub = 0x00000002},
[CPUID_8000001D_00000003_CACHE_PROPERTIES_END]
= {.func = 0x8000001d, .sub = 0x00000003},
[CPUID_8000001D_00000004_CACHE_PROPERTIES_DONE]
= {.func = 0x8000001d, .sub = 0x00000004},
[CPUID_8000001E_00000000_EXTENDED_IDENTIFIERS]
= {.func = 0x8000001e, .sub = 0x00000000},
/* AMD Family 17h */
[CPUID_8000001F_00000000_SECURE_ENCRYPTION]
= {.func = 0x8000001f, .sub = 0x00000000},
[CPUID_80000020_00000000_MBE_SUB_LEAF]
= {.func = 0x80000020, .sub = 0x00000000},
[CPUID_80000020_00000001_MBE_SUB_LEAF]
= {.func = 0x80000020, .sub = 0x00000001},
/* AMD Family 19h */
[CPUID_80000021_00000000_EXTENDED_FEATURE_2]
= {.func = 0x80000021, .sub = 0x00000000},
/* x86 */
[CPUID_40000000_00000000_HYPERVISOR_VENDOR]
= {.func = 0x40000000, .sub = 0x00000000},
[CPUID_40000001_00000000_HYPERVISOR_INTERFACE]
= {.func = 0x40000001, .sub = 0x00000000},
[CPUID_40000002_00000000_HYPERVISOR_VERSION]
= {.func = 0x40000002, .sub = 0x00000000},
[CPUID_40000003_00000000_HYPERVISOR_FEATURES]
= {.func = 0x40000003, .sub = 0x00000000},
[CPUID_40000004_00000000_HYPERV_REQUIREMENTS]
= {.func = 0x40000004, .sub = 0x00000000},
[CPUID_40000005_00000000_HYPERVISOR_LIMITS]
= {.func = 0x40000005, .sub = 0x00000000},
[CPUID_40000006_00000000_HYPERVISOR_EXPLOITS]