ECE3056 - Cache Model

This program models a sequence of write misses, hits, on varying sizes of an LRU cache to be used for realization of cache design and tradeoffs in structure and access parameters. This was written for ECE_3056, an advanced junior level class at the Georgia Institute of Technology.

Contributing

• Template and shell: ECE_3056 Professor Sudhakar Yalamanchili

Authors

• Stephen Via - Initial work - svia3